4-mbit (256k x 16) pseudo static ram cyk256k16mccb mobl3? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05585 rev. *f revised october 18, 2006 features ? wide voltage range: 2.70v?3.30v ? access time: 55 ns, 60 ns and 70 ns ? ultra-low active power ? typical active current: 1 ma @ f = 1 mhz ? typical active current: 8 ma @ f = f max (70-ns speed) ? ultra low standby power ? automatic power-down when deselected ? cmos for optimum speed/power ? offered in a 48-ball bga package functional description [1] the cyk256k16mccb is a high-performance cmos pseudo static ram organized as 256k words by 16 bits that supports an asynchronous memory inte rface. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device can be put into standby mode when deselected (ce high or both bhe and ble are high). the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected (ce high), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high), or during a write operation (ce low and we low). writing to the device is accomplished by taking chip enable (ce low) and write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ) is written into the location specified on the address pins (a 0 through a 17 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 17 ). reading from the device is accomplished by taking chip enable (ce low) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . refer to the truth table for a complete description of read and write modes. note: 1. for best practice recommendations, pleas e refer to the cy application note system design guidelines on http://www.cypress.com. logic block diagram 256k 16 ram array i/o0 ? i/o7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o8 ? i/o15 we ble bhe a 16 a 0 a 1 a 9 a 10 power- down circuit bhe ble ce ce a 17 [+] feedback [+] feedback
cyk256k16mccb mobl3? document #: 38-05585 rev. *f page 2 of 10 pin configuration [2, 3, 4] vfbga product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1mhz f = f max min. typ. [5] max. typ. [5] max. typ. [5] max. typ. [5] max. cyk256k16mccb 2.70 3.0 3.30 55 1 5 14 22 17 40 60 70 8 15 notes: 2. ball h1, g2 and ball h6 for the vfbga package can be used to upgrade to an 8-mbit, 16-mbit and 32-mbit density, respectively. 3. nc ?no connect? ? not connected internally to the die. 4. dnu (do not use) pins have to be left floating or tied to vss to ensure proper application. 5. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25c. we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe vss a 7 i/o 0 bhe nc a 17 a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 3 2 6 5 4 1 d e b a c f g h top view a 16 dnu vcc nc nc nc [+] feedback [+] feedback
cyk256k16mccb mobl3? document #: 38-05585 rev. *f page 3 of 10 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ..... ?65c to + 150c ambient temperature with power applied .......... .............. .............. ..... ?55c to + 125c supply voltage to ground potent ial ................ ?0.4v to 4.6v dc voltage applied to outputs in high-z state [6, 7, 8] ....................................... ?0.4v to 3.7v dc input voltage [6, 7, 8] ....................................?0.4v to 3.7v output current into outputs (low) ............................ 20 ma static discharge voltage ........ ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current .................................................... > 200 ma operating range range ambient temperature v cc industrial ?25c to +85c 2.70v to 3.30v electrical characteristics over the operating range parameter description test conditions cyk256k16mccb -55, 60, 70 unit min. typ. [5] max. v cc supply voltage 2.7 3.0 3.3 v v oh output high voltage i oh = ?0.1 ma v cc = 2.70v v cc ? 0.4 v v ol output low voltage i ol = 0.1 ma v cc = 2.70v 0.4 v v ih input high voltage 0.8 * vcc v cc + 0.4v v v il input low voltage ?0.4 0.6 v i ix input leakage current gnd < v in < v cc ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma cmos levels 14 for ?55 14 for ?60 8 for ?70 22 for ?55 22 for ?60 15 for ?70 ma f = 1 mhz 1 for all speeds 5 for all speeds ma i sb1 automatic ce power-down current?cmos inputs ce > v cc ? 0.2v v in > v cc ?0.2v, v in < 0.2v) f = f max (address and data only), f = 0 (oe , we , bhe and ble ), v cc = 3.30v v cc = 3.3v 150 250 a i sb2 automatic ce power-down current?cmos inputs ce > v cc ? 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.30v v cc = 3.3v 17 40 a thermal resistance [9] parameter description test conditions bga unit ja thermal resistance (junction to ambient) te st conditions follow standard test methods and procedures for measuring thermal impedence, per eia/jesd51. 55 c/w jc thermal resistance (junction to case) 17 c/w capacitance [9] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 8pf c out output capacitance 8 pf notes: 6. v il(min) = ?0.5v for pulse durations less than 20 ns. 7. v ih(max) = v cc + 0.5v for pulse durations less than 20 ns. 8. overshoot and undershoot spec ifications are characterized and are not 100% tested. 9. tested initially and after any design or process changes that may affect these parameters. [+] feedback [+] feedback
cyk256k16mccb mobl3? document #: 38-05585 rev. *f page 4 of 10 ac test loads and waveforms parameters 3.0v v cc unit r1 22000 ? r2 22000 ? r th 11000 ? v th 1.50 v switching characteristics over the operating range [10] parameter description 55 ns [14] 60 ns 70 ns unit min. max. min. max. min. max. read cycle t rc read cycle time 55 60 70 ns t aa address to data valid 55 60 70 ns t oha data hold from address change 5 8 10 ns t ace ce low to data valid 55 60 70 ns t doe oe low to data valid 25 25 35 ns t lzoe oe low to low z [11, 13] 555ns t hzoe oe high to high z [11, 13] 25 25 25 ns t lzce ce low to low z [11, 13] 225ns t hzce ce high to high z [11, 13] 25 25 25 ns t dbe ble/bhe low to data valid 55 60 70 ns t lzbe ble /bhe low to low z [11, 13] 555ns t hzbe ble /bhe high to high z [11, 13] 10 10 25 ns t sk [14] address skew 0 5 10 ns write cycle [12] t wc write cycle time 55 60 70 ns t sce ce low to write end 45 45 60 ns t aw address set-up to write end 45 45 55 ns t ha address hold from write end 0 0 0 ns t sa address set-up to write start 0 0 0 ns t pwe we pulse width 40 40 45 ns notes: 10. test conditions for all parameters other than tri-state paramete rs assume signal transition time of 1 ns/v, timing reference levels of v cc(typ) /2, input pulse levels of 0v to v cc(typ.) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? section. 11. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedance state. 12. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set-up and hold timing should be referenced to the edg e of the signal that terminates the write. 13. high-z and low-z parameters are characterized and are not 100% tested. 14. to achieve 55-ns performance, the read access should be ce controlled. in this case t ace is the critical parameter and t sk is satisfied when the addresses are stable prior to chip enable going active. for the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle. v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v th equivalentto: th venin equivalent all input pulses r th r1 [+] feedback [+] feedback
cyk256k16mccb mobl3? document #: 38-05585 rev. *f page 5 of 10 t bw ble /bhe low to write end 50 50 55 ns t sd data set-up to write end 25 25 25 ns t hd data hold from write end 0 0 0 ns t hzwe we low to high-z [11, 13] 25 25 25 ns t lzwe we high to low-z [11, 13] 555ns switching characteristics over the operating range [10] (continued) parameter description 55 ns [14] 60 ns 70 ns unit min. max. min. max. min. max. switching waveforms read cycle 1 (address transition controlled) [14, 15, 16] read cycle 2 (oe controlled) [14, 16] notes: 15. device is continuously selected. oe , ce = v il . 16. we is high for read cycle. address data out previous data valid data valid t rc t aa t oha t sk 50% 50% data valid t rc t ace t doe t lzoe t lzce high impedance t hzoe high oe ce i cc i sb impedance address v cc supply current t hzbe bhe / ble t lzbe t hzce data out t dbe t sk [+] feedback [+] feedback
cyk256k16mccb mobl3? document #: 38-05585 rev. *f page 6 of 10 write cycle 1 (we controlled) [12, 13, 17, 18, 19] write cycle 2 (ce controlled) [12, 13, 17, 18, 19] notes: 17. data i/o is high-impedance if oe > v ih . 18. if chip enable goes inactive with we = v ih , the output remains in a high-impedance state. 19. during this period in the data i/o waveform, the i/os coul d be in the output state and input signals should not be applied. switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data ce address we data i/o oe bhe / ble t bw don?t care t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data ce address we data i/o oe don?t care bhe /ble t bw t sa [+] feedback [+] feedback
cyk256k16mccb mobl3? document #: 38-05585 rev. *f page 7 of 10 write cycle 3 (we controlled, oe low) [18, 19] write cycle 4 (bhe /ble controlled, oe low) [18, 19] switching waveforms (continued) valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o t bw bhe / ble don?t care t hd t sd t sa t ha t aw t wc valid data t bw t sce t pwe don?t care address ce bhe /ble we data i/o [+] feedback [+] feedback
cyk256k16mccb mobl3? document #: 38-05585 rev. *f page 8 of 10 truth table [20] ce we oe bhe ble inputs/outputs mode power h x x x x high z deselect/power-down standby (i sb ) x x x h h high z deselect/power-down standby (i sb ) l h l l l data out (i/o0 ? i/o15) read active (i cc ) l h l h l data out (i/o0 ? i/o7); high z (i/o8 ? i/o15) read active (i cc ) l h l l h high z (i/o0 ? i/o7); data out (i/o8 ? i/o15) read active (i cc ) l h h l h high z output disabled active (i cc ) l h h h l high z output disabled active (i cc ) l h h l l high z output disabled active (i cc ) l l x l l data in (i/o0 ? i/o15) write active (i cc ) l l x h l data in (i/o0 ? i/o7); high z (i/o8 ? i/o15) write active (i cc ) l l x l h high z (i/o0 ? i/o7); data in (i/o8 ? i/o15) write active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 55 cyk256k16mccbu-55bvi 51-85150 48-ball fine pitch bga (6 mm 8mm 1.0 mm) industrial CYK256K16MCBU-55BVXI 48-ball fine pitch bga (6 mm 8mm 1.0 mm) (pb-free) 60 cyk256k16mccbu-60bvi 51-85150 48-ball fine pitch bga (6 mm 8mm 1.0 mm) industrial 70 cyk256k16mccbu-70bvi 51-85150 48-ball fine pitch bga (6 mm 8mm 1.0 mm) industrial cyk256k16mcbu-70bvxi 48-ball fine pitch bga (6 mm 8mm 1.0 mm) (pb-free) note: 20. h = logic high, l = logic low, x = don?t care. [+] feedback [+] feedback
cyk256k16mccb mobl3? document #: 38-05585 rev. *f page 9 of 10 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. mobl is a registered trademark, and more battery life and mobl3 are trademarks, of cypress semiconductor corporation. all product and company names mention ed in this document may be the trademarks of their respective holders. package diagram a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 8.000.10 a 8.000.10 6.000.10 b 1.875 2.625 0.26 max. 48-ball vfbga (6 x 8 x 1 mm) (51-85150) 51-85150-*d [+] feedback [+] feedback
cyk256k16mccb mobl3? document #: 38-05585 rev. *f page 10 of 10 document history page document title: cyk256k16mccb mobl3?4- mbit (256k x 16) pseudo static ram document number: 38-05585 rev. ecn no. issue date orig. of change description of change ** 223482 see ecn ref new data sheet *a 234474 see ecn syt changed ball e3 on package pinout from nc to dnu *b 260330 see ecn pci changed from preliminary to final *c 298651 see ecn pci added 60-ns speed bin *d 314013 see ecn rkf added pb-free parts to the ordering information *e 397852 see ecn syt changed address of cypress se miconductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? changed typo in ordering code from cyk256k16mccb to cyk256k16mccbu in the ?ordering information? on page#8 updated the revision of package diagram of spec 51-85150 from *b to *d *f 522566 see ecn nxr changed v il max spec from 0.4 v to 0.6 v in dc electrical characteristics table [+] feedback [+] feedback
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